Josep Torrellas
Professor and Willett Faculty Scholar
Department of Computer Science at UIUC
IEEE Fellow
National Science Foundation Young Investigator Award, 1994
Ph.D. in Electrical Engineering, Stanford University, 1992
Chairman, IEEE Technical Committee on Computer Architecture
Department of Computer Science at UIUC
IEEE Fellow
National Science Foundation Young Investigator Award, 1994
Ph.D. in Electrical Engineering, Stanford University, 1992
Chairman, IEEE Technical Committee on Computer Architecture
- « Publications »
- « Curriculum Vitae »
- « Students Graduated»
Some Recent Publications:
- Facelift: Hiding and Slowing Down Aging in Multicores, MICRO, November 2008.
- EVAL: Utilizing Processors with Variation-Induced Timing Errors, MICRO, November 2008.
- DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently, ISCA, June 2008.
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, ISCA, June 2008.
- An Updated Evaluation of ReCycle, WDDD, June 2008.
- SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization, ASPLOS, March 2008.
Software Released:
- VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
- SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.
Research Interests:
Professor Torrellas leads The i-acoma Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The goal is to design high-performance multiprocessor computers that are very easy to program, inexpensive, and built out of commodity components.The main emphasis is on several areas:
- Multiprocessor organization and system design
- Speculative multithreading
- Hardware reliability and variability
- Support for software reliability
- Low-power design
- Old Projects
Professor Torrellas is also involved in the related project The Polaris parallelizing compiler.
Currently Teaching:
CS533: Parallel Computer Architectures.Contact Information
Josep Torrellas4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrellas@cs.uiuc.edu.
Administrative Assistant
Sheila Clark,Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-6621, fax 217-265-6582.
E-mail: sdclark@cs.uiuc.edu.